onbreak {resume}
transcript on

set PrefMain(saveLines) 50000
.main clear

if {[file exists rtl_work]} {
    vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work

# load designs

# insert files specific to your design here

vlog -sv -work rtl_work +define+SIMULATION SRAM_Controller.v
vlog -sv -work rtl_work tb_SRAM_Emulator.v
vlog -sv -work rtl_work Clock_100_PLL.v
vlog -sv -work rtl_work tb_InC.v
vlog -sv -work rtl_work InC.v
vlog -sv -work rtl_work Interpolation.v
vlog -sv -work rtl_work Mul32.v
vlog -sv -work rtl_work Even_Colour_Space_Conv.v
vlog -sv -work rtl_work Odd_Colour_Space_Conv.v

# specify library for simulation
vsim -t 100ps -L altera_mf_ver -lib rtl_work tb_InC

# Clear previous simulation
restart -f

view wave
add wave Clock_50

########################################################
# InC module
########################################################
add wave uut/state
add wave uut/substate
add wave -unsigned uut/column
add wave -unsigned uut/row
add wave uut/start
add wave uut/finish
add wave -hexadecimal uut/SRAM_Addr
add wave -hexadecimal uut/SRAM_Data
add wave -hexadecimal uut/SRAM_Write
add wave uut/we
add wave -hexadecimal uut/R_out_buf
add wave -hexadecimal uut/G_out_buf
add wave -hexadecimal uut/B_out_buf
add wave -hexadecimal uut/U_in_buf
add wave -hexadecimal uut/V_in_buf
add wave -hexadecimal uut/U_out_buf
add wave -hexadecimal uut/V_out_buf
add wave -hexadecimal uut/Y_reg
add wave -hexadecimal uut/UR
add wave -hexadecimal uut/VR
add wave uut/uIntStart
add wave uut/vIntStart
add wave uut/cscEStart
add wave uut/cscOStart

# run complete simulation
run -all

destroy .structure
destroy .signals
destroy .source

simstats
